1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of fabricating an electrode structure for a cylindrical capacitor in an integrated circuit, which can allow the resultant electrode structure to be formed substantially without having horn-like portions such that the leakage current in the capacitor can be minimized.
2. Description of Related Art
A computer system typically includes a central processing unit and a memory unit. Presently, DRAM (dynamic random access memory) is widely used as the primary memory of computer systems. A DRAM cell is typically composed of a transfer FET (field effect transistor) and a data storage capacitor. Whether a binary value of 1 or 0 is stored in a DRAM cell is dependent on whether the data storage capacitor of the DRAM cell stores electric charge or not.
In conventional DRAMs having a storage capacity less than 1 MB (megabit) of data, it is a customary practice to use a two-dimensional capacitor called a planar-type capacitor as the data storage capacitor. However, one drawback to the planar-type capacitor is that its structure takes up quite a large area on the wafer. The planar-type capacitor is therefore not suitable for DRAM devices that require a high level of integration. In large integration DRAMs such as the 4 MB or higher DRAMs, a three-dimensional capacitor called a stacked-type capacitor is typically used as the data storage capacitor. One example of the stacked-type capacitor is the so-called cylindrical capacitor.
FIGS. 1A-1F are schematic sectional diagrams used to depict the steps involved in a conventional method for fabricating an electrode structure for a cylindrical capacitor.
Referring first to FIG. 1A, the cylindrical capacitor is constructed on a semiconductor substrate 10. In this substrate 10, a plurality of source/drain regions (not shown) is formed, which regions are used to construct a transfer FET that is to be used in conjunction with the cylindrical capacitor to form a DRAM cell.
Subsequently, an insulating layer 12 is formed, preferably from silicon oxide, over the substrate 10 and then a contact window 14 is formed in the insulating layer 12 to expose one source/drain region (not shown) in the substrate 10. After this, a conductive layer 16 is formed, preferably from polysilicon, over the insulating layer 12, which also fills the entire contact window 14 in the insulating layer 12.
Referring next to FIG. 1B, in the subsequent step, a photoresist layer 18 is formed through a photolithographic and etching process at a predefined location on the conductive layer 16 directly above the contact window 14.
Referring further to FIG. 1C, an etching process is then performed on the wafer, with the photoresist layer 18 serving as mask, so as to etch away part of the conductive layer 16 to a predetermined depth. Through this process, the part of the conductive layer 16 that is laid directly beneath the masking photoresist layer 18 forms a protruding portion 20. After this, the entire photoresist layer 18 is removed.
Referring next to FIG. 1D, in the subsequent step, a sidewall spacer 22 is formed on the sidewall of the protruding portion 20 of the conductive layer 16. This sidewall spacer 22 can be formed by, for example, first depositing an insulating layer over the entire top surface of the wafer; and then performing an anisotropic etch-back process on the insulating layer. Through the anisotropic etch-back process, the remaining part of the insulating layer serves as the sidewall spacer 22.
Referring further to FIG. 1E, in the subsequent step, an etching process is performed on the wafer, with the sidewall spacer 22 serving as mask, until all of the conductive layer 16 other than the part lying directly beneath the protruded portion 20 and sidewall spacer 22 is entirely etched away (i.e., until the top surface of the insulating layer 12 is exposed). Through this etching process, however, the part of the conductive layer 16 that is laid directly beneath the sidewall spacer 22 is substantially intact, and moreover a small thickness of the conductive layer 16 still remains over the contact window 14.
Referring further to FIG. 1F, in the subsequent step, the sidewall spacer 22 is removed through, for example, a wet-etching process. The remaining part of the conductive layer, here designated by the reference numeral 16a, serves as a bottom electrode structure that can be later used to form a complete cylindrical capacitor by further forming a dielectric layer (not shown) over the conductive layer 16a and then an upper electrode structure (not shown) over the dielectric layer (not shown).
One drawback to the foregoing electrode structure 16a, however, is that it is formed with horn-like portions 24 that can act as a particle source when the wafer is later submerged in an acid solution during the process for forming the dielectric layer. These horn-like portions 24 can easily cause the resultant cylindrical capacitor to suffer from a large leakage current.